1. Field of the Invention
The present invention relates to loosely-coupled multiprocessor systems in which a plurality of processors having memories, in which memory spaces independent from one another are configured, are connected.
2. Description of the Related Art
Conventionally, there is a tightly-coupled multiprocessor system in which a plurality of processors share a main memory. Such a multiprocessor system can be configured at relatively low cost by adopting a processor applicable to a symmetric multi processing configuration (SMP) such as an x86 CPU of Intel Corporation and Advance Micro Devices, Inc. The processor is often adopted in a system that is not only required to be excellent in performance but also required to be reduced in a total cost of ownership (TCO). However, in the tightly-coupled multiprocessor system, a larger load is imposed on the memory as the number of processors increases. Therefore, although the performance of the entire system is improved to some extent according to the increase in the number of processors, even if the number of processors is further increased, the performance of the entire system is not so improved but saturated because of difficulty in accessing the memory. In other words, the tightly-coupled multiprocessor system is suitable for a relatively small-size system but is not adaptable to a large-size multiprocessor system mounted with one-hundred or more processors.
On the other hand, there is a loosely-coupled multiprocessor system in which a plurality of processors include main memories independent from one another (see, for example, Japanese Patent Application Laid-open No. 2001-331457). In such a multiprocessor system, even if the number of processors increases, accesses do not concentrate on the memories and the performance of the entire system is not saturated. Therefore, the loosely-coupled multiprocessor system is adaptable to a large-size multiprocessor system mounted with a large number of processors.
However, in the loosely-coupled multiprocessor system, a communication band and a delay time (latency) among the processors affect the performance of the system. This is because, assuming that there is a task such as a simulation to be executed by the multiprocessor system, even if the task is subdivided and allocated to the respective processors, there are often some relation and dependency among the subdivided tasks. Therefore, it is necessary to exchange information such as a calculation result among the processors. To allow the processors to communicate with one another, interfaces such as Ethernet (a registered trademark), InifiBand (a registered trademark), and Myrinet (a registered trademark) have been used. However, Ethernet has latency during communication. In other words, after a process operating on a processor of a transmission source transmits data, it takes long for a process operating on a processor on a reception side to receive the data. Further, a load of protocol processing such as TCP/IP in performing communication is heavy. If latency is long during communication, for example, when data is frequently exchanged among the processors, a communication overhead increases and the performance of the entire system falls. The heavy load of the protocol processing means that the precious performance of a CPU is wastefully consumed for processing other than a primary object of the CPU (e.g., simulation calculation). InifiBand and Myrinet have an advantage that a processing load on a CPU is light because latency is short and protocol processing is performed by hardware. However, interface cards for using InifiBand and Myrinet are extremely expensive because the interface cards are high in function and performance compared with those for Ethernet. Therefore, InifiBand and Myrinet are not often adopted in multiprocessor systems required to be reduced in cost. In general, a shared memory programming model is used to exchange a large amount of data among the processes in the tightly-coupled multiprocessor system. However, because InifiBand and Myrinet are merely high-speed communication means, it is rather difficult to realize a shared memory function on these interfaces. Therefore, when software developed for the tightly-coupled multiprocessor system is transitioned to the loosely-coupled multiprocessor system, a source code is rewritten. As a result, development efficiency for the software falls.
Therefore, there is a demand for a loosely-coupled multiprocessor system having high scalability of performance in which latency is short and a processing load on a CPU is relatively light. It is also desired to suppress a fall in development efficiency for software as much as possible.